X-ES XPedite6401 now available with NXP Arm-based QorIQ processors

Extreme Engineering Solutions (X-ES) has added
the NXP QorIQ LS1046A and LS1026A processors to the XPedite6401 XMC/PMC
mezzanine module. With the introduction of the NXP Arm A72 core processors, the
XPedite6401 now has up to four 64-bit ARM Cortex-A72 cores, extending the
available processor range and enabling support for a scalable low-power to
high-performance embedded computing solution within a single product design.

Layerscape LS1046A processor delivers high power and scalability

The XPedite6401 is an X-ES XMC/PrPMC mezzanine
module that supports an NXP LS1046A processor with up to four 64-bit Arm
Cortex-A72 cores with packet processing acceleration and high-speed
peripherals. Considered the most powerful NXP Arm core processor on the market
to date, the LS1046A processor delivers best-in-class performance in excess of
32,000 CoreMarks. By providing excellent networking performance and flexible I/O
options in a single System-on-Chip (SoC) design, it is well suited for embedded
computing applications ranging from Small Form Factor (SFF) networking to
security appliances.

Key features of the LS1046A processor include 23
x 23 mm package; pin-compatibility with the LS1043A and LS1088A SoCs allowing
users to scale the performance of the XPedite6401 from two to eight A53 cores
all the way up to four A72 cores; and high power-to-performance flexibility
allowing the XPedite6401 to be easily tailored to specific project requirements
and even upgraded from a lower level processor to meet evolving computing

The XPedite6401’s P16 connector provides
access to an array of I/O from the processor, maximising performance in a small
package design. It supports up to two 10GBASE-KR Ethernet ports, two 1000BASE-X
Ethernet ports or eight Ethernet ports through two QSGMII interfaces, one SATA
port capable of 6 Gb/s, and one USB 3.0 port.

features for trusted computing

NXP’s Trust Architecture is integrated into
all Layerscape devices, including support for Secure Boot, memory access
control/ strong partitioning, persistent storage, security state monitoring,
master secrets, security violation detection, and secure debug. Secure Boot
prevents inauthentic code from executing by verifying software against a
device-specific, one-time programmable master key while the processor remains
in a secure state, thereby preventing data extraction. The features of NXP’s
Trust Architecture expand the capabilities of XPedite6401 for high security

X-ES offers a turnkey Secure Boot
implementation package for all their NXP Layerscape processor-based hardware.
The Secure Boot package simplifies the code signing process for the customer,
providing the NXP Code Signing Tool as well as a revised U-Boot bootloader
adding the ability to validate images that are signed for X-ES processor

X-ES is represented in Australia and New Zealand by Metromatics

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