AFTER months of searching, Electronics News has found the best examples of innovative Australian and New Zealand electronics engineering to highlight in the 2006 EDN Innovation Awards.
A stellar group of judges has also been assembled to select the best of the best. The judging panel for this year comprises Emeritus Professor Trevor Cole from the University of Sydney’s School of Electrical and Information Engineering; Matthew Henderson, managing director of Australian Technology Connections; Dr Alex Zelinsky, director of the ; and Steven Keeping, Electronics News contributing editor.
All of this would not be possible without the support of the sponsors – , , , , , , – and the endorsement of industry organisations – the and Electronics Industry Association.
The finalists listed below are now in the running for the Best Application of Programmable Logic award, sponsored by Braemac. The winner will be announced during a gala dinner on 5 July as part of the 2006 Technology Futures Conference at the Melbourne . They will also be listed in the August issue of Electronics News.
Liam Bathgate; Tenix Defence; Digital Radio Frequency Processor
The Digital Radio Frequency Processor (DRFP) provides a capability that previously required a number of separate units, can be easily programmed by users to perform a wide range of tasks, and can be readily incorporated in a computer network. With a unique dual receive and transmit capability, its function is to digitally acquire, manipulate and synthesise radio frequency signals used in applications like electronic warfare, communications and radars. The signals can then to be used for surveillance and reconnaissance, threat detection and deception – such as jamming an opponent’s communications or confusing radar systems. The DRFP uses a leading-edge field programmable gate array, a complex printed circuit board and a general purpose CPU. It is a VME64x form-factor, two-slot width card. All analogue and application communications interfaces are on the front panel.
Dr John Williams; ; Reconfigurable scalable computer
A team of electronics engineers from UQ is building the software operating system for NASA’s Reconfigurable Scaleable Computing (RSC) project. RSC provides a user-programmable reconfigurable fabric built from SRAM-based FPGAs coupled with all the resources needed to support development and implementation of space applications. Since the fabric of a reconfigurable system can change from mission to mission, the hardware can be reused over and over again with little or no redesign. The UQ team has been modifying Linux to run on this reconfigurable hardware, and has freely released the work to the public, which was how NASA became aware of the group’s expertise.
Paul Dunn; CSIRO Manufacturing & Infrastructure Technology; Hybrid Modular Processing System (HYMOD)
The HYMOD project aims to develop new high-speed parallel processor modules primarily, but not exclusively, for machine vision. At its core is a Xilinx FPGA, with four full-duplex 1Gb/s high-speed serial links radiating from it. The FPGA has its own memory resources, and is closely coupled to a MPC8260 PowerPC processor. This 133MHz processor has 64Mb of main memory and 32Mb of flash ROM. There are two variants of this basic design. The HYMOD CLP Module features a two million gate Xilinx Virtex-II FPGA for parallel data processing directly connected to up to 24Mb of dedicated ZBT SRAM. The HYMOD IO Module has a smaller FPGA and less memory, but can plug into a range of mezzanine modules for specialised IO.
Tim Trewinnard; ; NEC digital storage unit
In 2005, Bluewater Systems released a digital storage unit (DSU) to replace the traditional magnetic tape drives used in NEC telephone switches. Controlled by a 400MHz ARM processor, the product uses an FPGA to enable it to work with a range of proprietary interfaces used on telephone switches. By using the FPGA to emulate the timings and commands expected by the switches, the product is able to operate as a plug-and-play solution for a range of switch models. The FPGA and other associated hardware design elements were selected from an existing CPU module design that the company was developing in parallel. This module, the Snapper 255, included both the microprocessor required to control the overall solution and an Altera FPGA. Rather than use the module directly, the design was integrated into the DSU PCB within two weeks of development time.