The ever-rising popularity of mobile phones and assorted wireless interconnects has reinvigorated the use of RF and analogue circuits. Consequently, mixed-signal SOCs (systems on chips) are here to stay.
Unfortunately, that means the complexity of top-level validation is also here to stay. Designers now attribute the most common errors in SOCs to a mix of human error and a lack of comprehensive validation. The most commonplace errors in this vein are errors in interconnection, failure to test all possible modes of operation, polarity inversion of control signals, and errors with transposed digital buses. You can also attribute a lot of these problems to a lack of a single comprehensive validation method.
IC design has traditionally been in two camps: analogue and digital. Designers build most digital circuits behaviourally in RTL code with automated synthesis and most analogue circuits using TLD (transistor-level-design) tools, including schematics and a Spice tool. Neither method is completely ideal for full system validation. Design validation in Spice is painstakingly slow or simply doesn't converge, whereas digital simulators have no graceful way of dealing with analogue- and mixed-signal functions. You can approach the simulation and validation problem in a number of ways, all having strengths and weaknesses. However, design complexity and the amount of analogue versus digital components make some methods impractical.
All analogue
In an all-analogue approach, you use a Spice simulation, which defines everything as transistors. The all-analogue approach works well for small designs, sub-blocks of a larger system, or individuals with lots of time to waste. Low-dropout regulators, op amps, comparators, and other commodity ICs come to mind here. Professional versions of Spice, including Cadence's Spectre, Mentor Graphics' Eldo, Synopsys' HSpice, and Simucad's SmartSpice, all attempt to speed things up.
However, most SOC designs require a lot of simulation. Design and transistor-model complexity are outpacing computer speeds for simulation. Consider that the BSIM (Berkeley Short-Channel IGFET Model) 4.2 transistor model has more than 230 parameters, and designs with 1 million transistors are part of the challenge.
Spice's ability to simultaneously solve equations and do floating-point math prevents quick simulations of these complex structures. When you add corner testing and multimode operations into the mix, the all-analogue methodology is simply not viable. However, the analogue methodology is still viable for developing the small analogue sub-blocks in an SOC. Also, any necessary frequency-domain analysis must remain all-analogue due to the fact that designers simulate digital systems only in the time domain.
All-analogue, fast spice
To help speed analogue development, a number of companies have developed "fast-Spice" tools. These tools expedite simulation but sacrifice accuracy. Common fast-Spice techniques include: model simplification, relaxing error tolerances, lookup-table methods, event-driven methods that ignore inactive circuits, hierarchy, better simultaneous equation-solving methods, variable time-steps, and design partitioning.
Most tools interactively trade accuracy for execution time. Designers can make adjustments depending on the accuracy they require for a given portion of the design they are simulating.
However, at the heart of the method, the tools define all the circuits at the transistor level. This approach might improve simulation time, but any significant digital content or large amounts of analogue circuitry make this method quickly nonviable. Anything with digital gates should use RTL-simulation methods. Thus, fast-Spice tools are more valuable as part of mixed-mode-simulation methods.
Mixed mode
In mixed-mode simulation, designers define analogue circuits as transistors and digital circuits as RTL. This method is viable in limited situations but often chokes if your design contains a significant amount of analogue content. Virtually any transistor-level content greatly slows the process. Early analogue/digital co-simulation products comprised two simulators with a method of transferring information between them.
Some simulators attempt to improve speed and ease of use, but, no matter how you configured them, number crunching with Spice makes things run slowly. Designs employing a mix of ADCs, DACs, and PLLs do not simulate efficiently with this method, but this approach is valuable when you are developing smaller, mixed-signal blocks.
With no efficient way to simulate larger designs with transistor-level tools, the design industry developed ABMs (analogue behavioural models), such as Verilog-A, Verilog-AMS, and VHDL-AMS, to speed simulation.
Minimising the need for floating-point math, removing the use of complex-transistor models, and providing functional definitions that sidestep the details of transistor-level implementation all combine to expedite simulations.
Accuracy of the behavioural model is a manageable concern. In this method, each ABM needs to have a validation path back to the TLD. System-level designers perform most first-pass ABMs to a mathematical ideal.
Design entry is currently language-driven, with Verilog-A, Verilog-AMS, and VHDL-AMS being the dominant tools. The use of HDL-based tools implies that the orientation is to the digital designer who writes code. Successful analogue simulation requires knowledge of the subtle aspects of circuits, and many analogue designers don't want to write code. The solution for this problem is simple although not readily available: a schematic-entry tool for ABM development. Conceptually, this tool would be similar to The MathWorks' Simulink environment, which serves as a tool for the creation of Matlab code.
One start-up (Reference 4) is attempting to develop such a tool, so options are becoming available. Designers will most likely use either the HDL or the schematic methods. For now, however, designers wishing to use ABMs need coding skills. The skills are easy to acquire, and numerous examples are available (Reference 5.)
Mixed level and mode
Using a mix of ABMs, TLD, and RTL digital becomes both mixed-mode and mixed-level simulation. This type of simulation is a useful approach because it allows you to behaviourally expedite things while optimising TLD. The behavioural blocks help create the testbench for the transistor-level section.
For example, when designing a charge pump in a PLL, using an ABM voltage-controlled oscillator and an RTL-feedback divider considerably expedites simulation. Being able to close the feedback loop allows easier optimisation of the device.
The selective use of ABMs during this process implies that a full set of these models will be available as the block-by-block design nears completion. With these models in place, designers can do a fully behavioural top-level simulation. With complex designs, designers should avoid using transistor-level design at the top level.
Current-mode simulation
A technique for determining timing delay in digital designs, current-based modelling, does not apply to analogue design, because simulation tools need to solve all fundamentals, including Ohm's Law, Kirchoff's Voltage Law, Kirchoff's Current Law, V=LdI/dt, I=CdV/dt, I=dq/dt, and q=CV, for full Spice accuracy. According to CK Kumar, product-marketing manager at Nascentric, current-based modelling is "valuable for analogue behaviour of digital circuits" but does not provide a complete analogue-design-tool set, as most Spice tools do.
Top down vs. bottom up
Designers today typically employ a top-down- or a bottom-up-design method (Figure 1). Top-down design gets a lot of buzz about being the "correct" way to develop chips. In this method, designers develop a block-level architecture with RTL or ESL (electronic-system-level) functional definitions and first-order ABMs for analogue- and mixed-signal structures.
The typical top-down designer works from either a system or a digital perspective. Designers have been successful using the method for large SOCs, but the weakness in top-down design is that designers must validate the ABM-to-analogue-TLD correlation and frequently are unaware of the nonideal nature of the TLD. Bottom-up design suits TLD, in which designers manually piece together each functional block to create amplifiers, ADCs, and PLLs. This method far predates the SOC era.
All mixed-signal chips combine top-down and bottom-up methods. The important thing is getting them to properly meet in the middle with an accurate ABM to represent the TLD.
ABM-to-TLD correlation
Designers need to ensure that silicon correlates to Spice models, Spice models correlate to a simulation netlist, and Spice simulation correlates to an ABM (Figure 2.) All of these items are issues because lack of correlation breaks the chain necessary for maintaining accuracy.
Many problems arise from inaccurate foundry models, and designers frequently omit implicit items from simulation netlists, such as package and bonding models, component mismatch, noise parameters, and parasitic coupling, and the Spice model, consequently, is either incomplete or inaccurate. The step that is most often troublesome is Spice simulation to ABM correlation. Designers often overlook a mismatch in this step.
An all-too-common example of this omission occurs when an "ideal" DAC in a top-level design runs well through simulation. But when the design undergoes manufacturing, the DAC causes large current spikes on the power when it is clocking, or it takes too long to power up.
Much debate exists in the industry about the amount of design detail and quality designers need to make sufficiently accurate ABMs.
Running a testbench with TLD and ABM while developing subsections of a design can give designers an interactive comparison of the two models. Top-down design implies that design teams have created an ABM before TLD takes place, so designers must ensure that the final ABM and TLD plug and play in the same way. Designers can add even more characteristics to ABMs to quantify the interaction of blocks and ensure that their ABMs thoroughly validate their designs. Some industry participants think that design teams should even create transistor-level ABMs, but others see transistor-level ABMs as redundant. Going to this level of detail puts designers in the "too-complex-to-simulate" cage from which they are trying to escape. They need an accurate, functional black-box model. Beyond digital interconnect and ideal functioning, designers can add other components to their black-box ABMs to improve their quality.
Latency is another factor, because a delay always occurs from the input to the output of a circuit. A delay similar to that of the TLD is appropriate. Undetermined state periods, including mode switching, PLL-acquisition times, and the like can lead to "output-not-stable" scenarios. A complex model could mimic these conditions, but conditional error flagging during those periods should suffice. Designers need to check power cycling in the TLD for suitable behaviour. After that, the ABM can use error flagging for a predetermined period whenever the power supply or a power-down control changes state. Designers need to create conditional statements that monitor the acceptable range of power and ground voltages. These languages support the concepts of "analogue events" and "event monitoring." In addition, conditional statements monitor the stimulus and loading of the pins of the ABM block. The intent is to provide enough information to validate interconnection and proper functions. Designers need to check each small block in Spice, as well, and to balance the model's complexity with how much simulation time they need to run the more complex models.
Systematic testing and verification
If designers use top-level verification, they must keep track of multiple models of the same blocks, model correlation, multiple modes of operation, multiple testing scenarios, revision control, and the associated database management. Depending on the complexity of the design, designers may find that manually performing these tasks can be error-prone, cumbersome, or simply impossible to track. Ken Kundert, one of the founders of Designer's Guide Consulting, specialises in the verification of large mixed-signal chips. While at Cadence, Kundert led the development of Spectre, SpectreHDL, and SpectreRF. He has also been involved in the definition of Verilog-AMS, Verilog-A, and VHDL-AMS modelling languages. Due to the complexity of the process, Kundert's approach includes use of automation and a complete set of ABMs, which results in a more efficient process (Figure 3.) Kundert's approach maximises the use of software automation, because validation coexists with, rather than is merely a part of, the design flow.
Key concepts in the methodology include a verification plan that defines the models, modes of operation, input stimulus and acceptable outputs; a modelling plan that defines the necessary HDL and ABM models; and a top-level model that becomes an executable specification, which demonstrates the functions and features of the final chip.
The methodology also includes a simulation plan that itemises the tests to be run, the appropriate configuration in each test run; a self-checking testbench for model selection, providing stimulus and response monitoring and parametric pass/fail decisions; and regression testing to ensure that design progress and modifications do not corrupt design integrity and to swap small TLDs with ABMs so that model correlation remains unbroken.
You can find a comprehensive description of these concepts on the Designer's Guide Web site, but note that it provides only top-level validation. If you use the approach, you need to run TLDs through a complete set of tests before bringing them into the top-level system. The approach does not consider process, voltage, temperature, statistical variance, mismatch, noise, and linearity.
Using the approach requires designers to broaden their skills, write models, and understand control and test and verification definition.
In conclusion, insufficient system validation and top-level chip validation now cause most problems in SOCs. Spice-level validation is more accurate than using simplified ABMs, but Spice simulation is too slow, and most design groups lack the computational power necessary to make it practical to boost Spice simulation and make transistor-level validation of large SOCs.
Instead, designers are now developing methods to validate their large designs. A popular choice is to use ABMs, which range in complexity from simple, ideal structures to highly detailed Spice equivalents.
Of these ABM approaches, perhaps the most effective is the black-box equivalent in which the ABM and TLD have similar stimulus-response characteristics. Designers can effectively perform ABM-to-TLD validation on much smaller blocks. For SOCs, however, they should bring the system together with ABMs and multimode, multilevel methods.
Automating the validation as a separate procedure outside the design flow is a valuable way to expedite the process, reduce errors, and provide a greater probability of success.
References
IEEE International Behavioral Modeling and Simulation.
Conference, www.bmas-conf.org.
www.verilog.org/verilog-ams.
Lynguent, www.lynguent.com.
Designer’s Guide Consulting, www.designersguide.com.
Effective Electrons, www.effectiveelectrons.com/foundrymodels.html.