Home > Centellax Modular 10G BER test systems available from TRIO Test & Measurement

Centellax Modular 10G BER test systems available from TRIO Test & Measurement

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article image Centellax Modular 10G BER test systems

The Centellax Modular 10G BER test system, available from TRIO  Test & Measurement, is designed for device characterisation, research and development testing, production testing, and general lab use. The system features a synthesiser that operates the BERT at bitrates from 500Mbps to 12.5Gbps, and enables stressed eye testing and spread-spectrum clocking. With the addition of modular hardware such as a 622Mbps-13.5Gbps clock recovery unit, the SB10 system can be configured to address a range of physical layer digital signal integrity test applications.

The base system allows physical-layer BER testing of single-ended or differential DUTs with operating rates from 500Mbps to 7Gbps. The system is GPIB controlled with a suite of features including PRBS pattern selection (PRBS7-31), electronic clock/data alignment, variable output voltages (0.6-3.6Vpp differential), and clock and sub-rate trigger outputs.

Options to the SB10 system enable operation from 500Mbps to 12.5Gbps, easily-controlled jitter injection, and spread spectrum clocking. Other modular hardware options can add clock recovery functionality from 500Mbps to 7Gbps (or to 12.5Gbps), and additional channel test capability. The SB10 system can support six BER test channels.

When outfitted with the extended synthesiser range and un-banded clock recovery unit, the SB10 system is suitable for testing higher-rate devices that induce signal distortion (for example, fibre loops). The clock recovery unit can also be used to test a signal generated at a remote site, where the full-rate data clock must be recovered to test BER.

The SB10 system has the following benefits and features:

  • Operates from 500Mbps to 12.5Gbps
  • Integrated jitter source for stressed eye testing
  • Spread Spectrum Clocking for compliance testing
  • Configurable with a clock recovery unit
  • Low-cost alternative
  • Modular solution allows functional additions later
  • Differential or single-ended connections to DUT
  • System controlled by GPIB remote interface
  • PRBS patterns: 7, 10, 15, 23, 31
  • Mark/space density (ratio of 0's to 1's): 1/2, 1/4, 1/8
  • Modular components: TG1B1-A: 0.5-12.5Gbps BERT, TG1C1-A: 7G/13G clock synthesiser and TR1C1-A: 7G/13G clock recovery unit

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