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Digital RF architecture cuts power and chip count

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Texas Instruments (TI) claims to have developed a wireless chip design architecture that exploits digital technology to simplify RF processing and reduce the cost and power of transmitting and receiving data wirelessly. It is further claimed to reduce required die area and system board space by up to 50 percent over traditional analogueue RF designs (see www.ti.com/digitalrf).

Called “Digital RF Processor” (DRP) architecture, TI says it has successfully integrated DRP into two Bluetooth products and a GSM/GPRS digital transceiver within its own R&D labs.

TI says DRP will help manufacturers to address the ever increasing demand for sophisticated features in mobile products including GPS location technology, local area networking capabilities and PDA-style applications.

TI says that since large blocks of CMOS logic can now operate at multi-GHz frequencies, sampled-data processing techniques, switched-capacitor filters, over-sampling converters, and digital signal processors can take over the role of analogueue amplifiers, filters, and mixers. TI claims that rather than an inefficient implementation of analogueue blocks in a digital process technology, with its DRP technology the analogue signal is over-sampled and processed in the digital domain. Since radio signals at the antenna are always analogue, however, a small amount of analogue processing is included in the DRP between the input and the first sampling function.

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