Tektronix, Inc. is now supplying a complete DDR2 protocol debug and validation solution for the TLA6000 Series Logic Analyzers. Including everything needed to validate and debug the operation of memory sub-systems in their designs, new options for the series are ideal for embedded engineers, even those who are not DDR2 experts.
Many embedded designs use DDR2 memory systems, commonly implemented as a bus on the microprocessor or as a block in an FPGA. The number of command, data and address signals and the complexity of the DDR2 protocol make visualising the operation for the bus and isolating potential problems difficult.
The new options for the TLA6000 Series consists of a set of tools designed to provide visibility to all address, data, and control signals including,
- Memory chip interposers that provide a way of probing embedded DDR memory systems and eliminates the need to design in probe access points. Working with the unique iCapture Analogue Mux feature of the TLA6000, the memory chip interposers provide a single probing solution for both the logic analyser and oscilloscope, saving time and minimising setup complexity.
- Protocol decode software showing all DDR2 transactions and providing triggering on DDR2 events.
- Sample point analysis software, automating the process of correctly configuring the TLA6000 Series to accurately sample the DDR2 signals.
- Protocol violation software that finds and reports any violation of the JEDEC-defined DDR2 protocol.
The new DDR2 option for the TLA6000 Series will be available globally beginning April 2011 and is supplied in Australia by TekMark Australia .