CEA-Leti and ST Microelectronics successfully demonstrated an ultra-wide-voltage range (UWVR) digital signal processor (DSP), based on 28nm ultra-thin body buried-oxide (UTBB) FD-SOI technology.
Produced by ST in their 28nm UTBB fully depleted SOI process technology, the device allows body-bias-voltage scaling from 0V to +2V, decreases minimum circuit operating voltage, and supports clock-frequency operation of 460MHzat 400mV.
The demonstrator achieves UWVR, greater energy efficiency, and unprecedented levels of efficiency in voltage and frequency using a combination of design techniques. ST and Leti developed and optimised standard cells libraries over the 0.275V-to-1.2V range: they offer ideal implementation results by virtue of non-overlapping power-performance characteristics. Among the optimised cells, fast pulse-triggered flip-flops are designed for variability tolerance at low voltage.
Additionally, on-chip timing-margin monitors dynamically adjust the clock frequency to a few per cent of the maximum operating frequency, independent of supply-voltage value, body-bias-voltage value, temperature, and process technology, enabling the DSP to exhibit 10x state-of-the-art operating frequency even at 0.4V.
Philippe Magarshack, Executive Vice President, Design Enablement Services, STMicroelectronics explains that UTBB FD-SOI technology delivers significant improvements in performance and power savings while minimising adjustments to existing design and manufacturing methodologies.
According to Thierry Collette, Division Vice President at Leti and head of the Design and Embedded Systems Platform, Leti’s ability to bridge innovation and upstream industry was key to developing advanced design techniques for leveraging intrinsic power and performance benefits of the technology, and then designing dedicated components that could ultimately suit Internet-of-Things end products.