The LAST POWER program sponsored by the European Union to develop a cost-effective and reliable technology for power electronics has announced its three-year program achievements that place Europe at the forefront of research and the commercialisation of energy-efficient devices for industrial and automotive applications, consumer electronics, renewable-energy conversion systems, and telecommunications.
Launched in April 2010 by the European Nanoelectronics Initiative Advisory Council (ENIAC) Joint Undertaking (JU), a public-private partnership in nanoelectronics, LAST POWER links private companies, universities and public research centres working in the field of wide bandgap semiconductors (SiC and GaN).
Consortium members include ST Microelectronics (Italy), project coordinator, LPE/ETC (Italy), Institute for Microelectronics and Microsystems of the National Research Council – IMM-CNR (Italy), Foundation for Research & Technology-Hellas - FORTH (Greece), NOVASiC (France), Consorzio Catania Ricerche - CCR (Italy), Institute of High Pressure Physics - Unipress (Poland), Universitàdella Calabria (Italy), SiCrystal (Germany), SEPS Technologies (Sweden), SenSiC (Sweden), Acreo (Sweden), and Aristotle University of Thessaloniki - AUTH (Greece).
The main achievements in SiC-related efforts were based on the demonstration by SiCrystal of large-area 4H-SiC substrates, 150mm in diameter with a cut-off angle of 2°-off axis. The material quality, both in crystal structure and surface roughness, is comparable with the standard 100mm 4°-off material available at the beginning of the project. At LPE/ETC, these substrates have been used for epitaxial growth of moderately doped epi-layers suitable for the fabrication of 600-1200V JBS (Junction Barrier Schottky) diodes and MOSFETs, due to the development of a novel CVD (Chemical Vapour Deposition) reactor for the growth on large-area (150mm) 4H-SiC.
The quality of the epitaxial layer enabled the fabrication of JBS (Junction Barrier Schottky) diodes in the industrial production line at ST Microelectronics. The characterisation of the first lots showed electrical performance comparable with the state-of-the-art 4°-off material. In this context, the fundamental technological step was the chemical mechanical polishing (CMP) process - StepSiC reclamation and planarization - implemented at NOVASiC, which is a key issue both for the preparation of the substrates before epitaxial growth and for the sub-nanometric control of the surface roughness of the device active layers. Within the project, the same company also developed epitaxial growth capability for both MOSFET and JFET devices.
Additional research activities in SiO2/SiC interfaces have been carried out in collaboration with ST and IMM-CNR to improve the channel mobility in 4H-SiC MOSFETs.
Finally, novel technological modules for high-temperature 4H-SiC JFETs and MOSFETs have been developed in collaboration between Acreo and FORTH, with the support of CCR for the study of moulding compounds and lead-free die-attach materials for reliable packaging solutions.
The LAST POWER project also researched the use of GaN-based devices in power electronics applications. LAST POWER worked with IMM-CNR, Unipress, and ST to develop the technological steps for normally-off AlGaN/GaN HEMTs with a ‘gold-free’ approach. The process modules are fully compatible with the device-fabrication flowchart set in the ST production line and are being integrated for HEMTs fabrication.
The fruitful interaction between the project partners working on material growth and device technology has enabled important steps towards monolithic integration of GaN-based and SiC-based devices, as both technologies have been successfully proven on 2°-off axis 4H-SiC substrates.