NEC Electronics has completed its three-year system-on-a-chip (SoC) design environment project ACE-2, which reduces the design time needed for complex SoC designs by up to two-thirds.
Designers using the new environment can reduce the time from system specification to tape-out for a 30 million gate SoC, while designers of next-generation ASIC SoCs will benefit from the environment’s system-level approach, according to NEC Electronics design execution centre general manager John Fallin.
“We have seen overall times reduced by up to two-thirds when the design flow is completely employed,” Fallin said.
“By addressing design issues at the system level, we have created an environment in which SoC designers can fine-tune designs quickly and easily and still have time to focus on their key competencies, namely overall system design and software development”.
Fallin said that in addition to two-thirds time savings, designers using the ACE-2 environment can also realise up to ten times faster verification speeds by performing simulation at the system level as opposed to the register transfer level.
Additionally, system level design techniques reduce hardware and software description requirements by as much as 90%, Fallin said.
NEC initiated the ACE-2 project in a bid to reduce turnaround time for ASIC SoC designs from an average of 450 engineering months to fewer than 150.
The initiative also involved a number of electronic design automation (EDA) companies in defining the new design methodology, Fallin added.