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New films may replace silicon dioxide

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Lathanum aluminate films may hold the key to one of the chip industry’s most urgent material problems by replacing silicon dioxide as a gate dielectric in MOSFET devices for 65nm and beyond.

Joint research between Motorola and China’s Nanjing University and the Institute of Physics has found that the properties of lathanum aluminate (LAO) and lathanum aluminum oxynitride (LAON) make it one of the strongest potential candidates for a new gate insulator in the smaller and faster CMOS ICs of the future.

Further, the materials could replace silicon dioxide as a gate dielectric in MOSFET devices for the 65 nanometer technology node and beyond without requiring extensive modification of the manufacturing equipment or process flow.

The 65nm process technology generation is one faced with critical roadblocks to the continued scaling of MOSFET devices.

The urgency comes from the fact that products based on 65nm could be as little as two generations away from the current generation, according to Motorola China R&D Institute director Karen Guo.

“Traditional materials will last one or two more generations, whereupon the industry will need a new material to continue down the path of faster, smaller, better electronics,” Guo said.

“We are very excited about the potential of this material and, while more research is required, lathanum aluminate is the most promising material we have seen.”

Many materials are currently under consideration within the industry as potential replacements for silicon dioxide as the gate dielectric material for 65nm CMOS technology.

However, most of these materials, which have a dielectric constant greater than 20, either are not thermodynamically stable in direct contact with silicon, or generate diffusion problems, which cause significant device performance degradation.

Guo said LAO and LAON demonstrate the best thermal stability among all known possible high dielectric constant (greater than 20) materials and can also be economically integrated into a traditional CMOS process flow.

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