MICROCHIP Technology has unveiled an industry first with the introduction of a 512k-bit I2C compatible serial EEPROM in an 8-pad dual flat no-lead (DFN) package.
The 24LC512, 24AA512, and 24FC512 are implemented in the company's advanced PMOS Electrically Erasable Cell (PEEC) process technology, enabling Microchip to offer high-density, low-power EEPROM devices in one of the thinnest packages available (0.9mm).
The 6mm x 5mm DFN package enables designers to use a 512k-bit serial EEPROM in low-headroom applications while reducing cost and increasing available board space.
Engineers currently using Microchip's 128k-bit or 256k-bit EEPROM memory devices now have the option to design in a higher-density EEPROM while retaining the same footprint. Additional packages include an 8-lead PDIP, 8-lead SOIC and 14-pin TSSOP.
Microchip's PEEC cell is the newest and most advanced generation in a long history of EEPROM innovation, quality and features.
Each of the three new devices has a page-write capability of up to 128 bytes and is capable of random reads throughout the entire array. Functional address lines allow up to eight devices on the same bus for a maximum of 4 megabits total address space.
Additional features include a fast write time of 5 milliseconds, a clock rate of 400kHz throughout the operating voltage of 2.5V - 5.5V and temperature range of -40°C to +85°C.
A high-speed version of this chip, the 24FC512, is capable of operating at a bus speed of 1MHz over the same voltage and temperature range. The low-voltage version (24AA512) operates between 1.8V - 5.5V, making it ideal for battery-powered applications.
The 24LC512 targets advanced, low-power applications including cell phones, caller ID, set-top boxes, pagers, Bluetooth technology or wireless accessories, consumer electronics, ISO cards and data acquisition systems.
Each of these markets requires high-density, compact, non-volatile memory for data storage.