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Model-Based Design for DO-254 from MathWorks

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 MathWorks  specialises in supplying different mathematical computing software.

SYDNEY, Australia 2010, MathWorks and Mentor Graphics has announced a joint collaboration to provide guidance on an integrated workflow for DO-254 compliance using model-based design. The approach combines tools from MathWorks and Mentor Graphics to support model-based design throughout different stages of the development process, including requirements definition and management, conceptual and detailed design, implementation and testing. Using this integrated workflow, aerospace engineers can verify earlier designs, implement in HDL faster, gain reuse of design and verification effort and easily manage requirements and test cases throughout the development process. 

In the new DO-254 workflow, engineers begin with Mentor Graphics ReqTracer to collect and manage requirements. From the requirements, an executable Simulink model is used to develop and explore a conceptual design including implementation details such as fixed-point effects.  Model blocks can be linked directly to requirements in ReqTracer to ensure traceability. Using verification and validation tools from MathWorks, engineers can perform functional testing and formal analysis at the conceptual model level. These design and verification capabilities allow engineers to ensure that the conceptual design is  tested, and is traceable to requirements and meets the necessary requirements. From this tested model, a detailed design in HDL can be automatically generated with Simulink HDL Coder.

From this stage onward, Mentor Graphics HDL Designer provides the primary environment for additional HDL development, code checking, code visualisations and reviews. Further verification of the detailed HDL design can be performed in the Mentor Graphics verification environment, leveraging the test vectors created at the model level, using tools such as ModelSim and Questa. Formal analysis is supported by 0-In Formal Verification, for HDL model checking and FormalPro, for logical equivalency checking. FPGA synthesis and integration with FPGA vendor place and route tools is accomplished by Precision RTL Plus. The verification results and synthesis constraint settings generated throughout the flow can be traced back to design and verification requirements using ReqTracer.

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