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Intel develops tri-gate transistor design

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Chip giant Intel has developed a three-dimensional tri-gate transistor design it will use to push the capacity of Moore’s Law beyond the 30-nanometer ceiling.

As transistors shrink to less than 30-nm, the increase in current leakage means that transistors require increasingly more power to function correctly, which generates unacceptable levels of heat.

This means that transistor design must move away from the traditional planar (flat) to non-planar 3D designs if the semiconductor industry is to maintain the pace of Moore’s Law beyond this decade, according to Intel components research lab director Dr Gerald Marcyk.

“Our research shows that below 30-nm, the basic physics of the flat, single-gate planar transistor leaks too much power to meet our future performance goals,” Marcyk said.

“The tri-gate transistor design will allow Intel to build ultra-small transistors that achieve high performance with low power and continue driving the pace of Moore’s Law.”

The tri-gate transistor employs a 3D structure similar to a raised plateau with vertical sides, which allows electronic signals to be sent along the top of the transistor and along both vertical sidewalls as well.

This effectively triples the area available for electrical signals to travel without taking up any more space, Dr Marcyk said.

The tr-gate itself is built on an ultra-thin layer of fully depleted silicon and incorporates a raised source and drain structure for low resistance – allowing the transistor to be driven with less power.

Marcyk said the design is also compatible with the future introduction of a high K gate dielectric for even lower leakage, and offers a promising approach for extending the TeraHertz transistor architecture, which Intel announced in December 2001.

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