The company is touting this integration as the first time the technologies have been combined into a single manufacturing process.
The 90nm process is the next generation after the 0.13 micron process, and is expected to be used in volume manufacturing by next year, according to Intel Technology and Manufacturing Group senior VP Sunlin Chou.
“While some are slowly transitioning production to 130nm (0.13-micron) process on 200mm wafers, we are moving ahead with the most advanced 90nm technology exclusively on 300mm wafers,” Chou said.
Chou said the new process will feature advanced transistors with gate lengths of 50nm and gate oxides only five atomic layers thick (1.2nm).
Current advanced transistors in P4 processors have gate lengths measuring 60nm, Chou said.
In addition to thin gate oxides, strained silicon will increase the speed of transistors by allowing current to flow through them more smoothly.
The process also integrates a new carbon-doped oxide (CDO) dielectric material that increases signal speed inside the chip and reduces chip power consumption.
Chou said the dielectric is implemented in a simple two-layer stack design to make it easier to manufacture.
Processor performance is also increased by integrating seven layers of high-speed copper interconnects – a feat made possible by a combination of 248 and 193nm wavelength lithography equipment.
While Intel expects to have three 300mm wafer fabs using the 90nm process by 2003, the first commercial chips made on the process are not due until the second half of next year.
This processor, codenamed Prescott, is based on the Intel NetBurst microarchitecture, according to Intel process architecture and integration director Mark Bohr.
“Intel’s 90nm process is very healthy today and we are routinely producing 300mm wafers and chips in our development fab,” Bohr said.
“By next year, we will be the first company to have a 90nm process in volume manufacturing.”