Hewlett-Packard researchers have created what they believe is a new way to design future nanoelectronic circuits using coding theory - an approach currently being used in certain maths, cryptography and telecommunications applications, the company reports.
The company believes that the result of using this approach could be nearly perfect manufacturing yields with equipment a thousand times less expensive than what might be required using future versions of current technologies.
“We have invented a completely new way of designing an electronic interconnect for nanoscale circuits using coding theory, which is commonly used in today’s digital cell phone systems and in deep-space probes,” says Stan Williams, HP senior fellow and director of Quantum Science Research at HP Labs, in a statement.
“By using a cross-bar architecture and adding 50 percent more wires as an ‘insurance policy’, we believe it will be possible to fabricate nanoelectronic circuits with nearly perfect yields even though the probability of broken components will be high,” he continues.
Williams said he believes future chips will have to rely at least in part on the crossbar architecture, in which a set of parallel nanoscale wires are laid atop another set of parallel wires at approximately a 90 degree angle, sandwiching a layer of electrically switchable material in between.
Where the material becomes trapped between the crossing wires, they can form a switch that represents a “1” or “0”, the basic building blocks of computer code.
HP admits future chips may be limited in the geometric complexity that can be created at the nanolevel because of problems with precision alignment, however, crossbar structures are highly regular and therefore relatively easier and less expensive to fabricate than the complex array of wires, transistors and other elements in today’s processors even though they require more space on the silicon substrate.
“We think the tradeoff of space versus manufacturing ease will become more an issue in the near future,” Williams adds.
Further, as sizes of electronic features get down to a few nanometers, it will become either physically impossible—or economically unfeasible—to produce absolutely perfect circuits with future chip manufacturers having to deal with the reality of defects.
HP’s approach involves enhancing a device known as a demultiplexer, which enables data to be read and written in a circuit by connecting the crossbar array of nanowires to a small number of conventional wires, the company explained.
By adding a few more conventional wires and using basic coding theory, HP researchers have shown that the demultiplexer will still work even if a significant number of the connections between the conventional wires and the nanowires are broken.
Phil Kuekes, a senior computer architect and one of the authors of the paper that details these findings explained that the approach is similar to giving a distinctive name to a restaurant host to be sure you hear your party called above the noise of the crowd.
“Instead of ‘the Jones party,’ you might put yourself down as ‘the John Paul Jones party.’ That way, when the host calls your name, you’ll hear it, even if every word doesn’t come through clearly,” Kuekes explains in the statement.
Using defect tolerance to replace the need to produce “perfect” chips could provide a huge cost advantage for chip manufacturers in the future, HP contends.
HP Labs said it has created working devices in the laboratory at the 30 nm half-pitch scale, which is about a third the size of today’s chips. The International Technology Roadmap for Silicon, the standard for the industry, predicts that chips using features at 32 nm half-pitch should be in production in seven to eight years.