Home > UMC and Synopsys tape out 14nm FinFET test chip

UMC and Synopsys tape out 14nm FinFET test chip

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article image UMC has successfully taped out its first test chip for its 14nm FinFET manufacturing process.
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United Microelectronics (UMC) has successfully taped out its first test chip for its 14nm FinFET manufacturing process, with the help of Synopsys DesignWare.

The FinFET oricess is generating significant interest due to its performance, power, intra-die variability and lower retention voltage over the planar CMOS process.

The process qualification chip will provide the firms with early silicon data, enabling UMC to tune its 14-nm FinFET process and Synopsys to refine its DesignWare IP portfolio for optimal power, performance and area.

It also provides data to enable better correlation of the FinFET simulation models to the silicon results. This is the first milestone of an ongoing collaboration to validate UMC's 14-nm FinFET processes using DesignWare IP solutions.

Synopsys' FinFET-ready DesignWare Logic Library IP portfolio consists of high-speed, high-density and low-power standard cell libraries that include multiple voltage threshold implementations and support multi-channel gate lengths to minimise leakage power.

The StarRC parasitic extraction tool offers advanced extraction capabilities at 14 nm, based on precise 3-D modeling of the new parasitics found in FinFET devices. Due to its unique ability to describe the exact silicon profile of FinFET transistors, StarRC's embedded field solver generates highly accurate device model parasitics which enable 14-nm IP developers to optimise their designs for maximum performance and lowest power.

While UMC lagged behind TSMC in the 28nm CMOS process, it hopes its collaborative development on the 14nm and 10nm FinFET processes will yield competitive results.

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