Hybrid Ethernet and Metro ADM chip
FUJITSU Microelectronics, represented in Australia by Crest Technologies , has released an ETHOS (ETHernet Over SDH/SONET) device for full-rate Gigabit Ethernet and E1/DS1 access in Metro and Access networks.
The first certified samples of ETHOS have been shipped to customers for development and system testing. Its system-on-chip design enables cost effective and compact customer located equipment. It is equally well-suited as the core device on Gigabit Ethernet interface cards in multiservice aggregation equipment.
The support for full-rate Gigabit Ethernet over protected SDH networks enables development of reliable, high-bandwidth network termination equipment. The standards-based SDH implementation enables integration into existing optical networks, while Virtual Concatenation and LCAS enable dynamic bandwidth allocation in steps of VT-1.5 or VC-12, VC-3 or VC-4, according to service demand for end-users.
ETHOS is designed for equipment in customer premises access or metro aggregation networks. Its dual access technologies make it suitable for equipment for the wireless and DSLAM backhaul infrastructure. It provides an upgrade path as the access network migrates from cell based over E1/DS1 or STM-1/OC-3, to packet based over Ethernet.
ETHOS is a fully integrated, single-chip, add-drop multiplexer. Four line ports at STM-4/OC-12 or STM-1/OC-3 are provided, each supporting direct connection to SFP modules. There are four E1/DS1 ports, and four Ethernet or Gigabit Ethernet ports on the access side, as well as higher and lower order cross-connect fabrics and a Telecom bus for port expansion. Ethernet frames are mapped via GFP, LAPS, or PPP, Virtual Concatenation and low latency LCAS.
The advanced feature set also includes an integrated system timing generator, Ethernet flow control, support for Jumbo frames, TCP friendly rate controllers for fine-grained bandwidth assignment. It also has packet insertion and extraction for next generation carrier class Ethernet applications.
ETHOS is designed in Fujitsu's 0.18 micron process and delivered in a 756-pin BGA-TE package. Support is available through datasheets, application notes, device model, reference design and software.
4-May-2005