AMPLE Communications, represented by Caelera , has announced its Harrier family of Frame Processors for the development of 10/100/1000 Ethernet enterprise and metropolitan area network systems.
The highly-integrated Harrier devices provide programmable, intelligent oversubscription to optimize existing network infrastructure and reduce the number of components required to enable a high density Ethernet solution.
The Harrier family consists of three aggregation devices: Harrier-24 with 24 10/100/1000 Ethernet ports; Harrier-12 with 12 10/100/1000 Ethernet ports; and Harrier-24LS with 24 10/100 ports.
Each device interoperates with off-the-shelf Ethernet physical layer devices via standard RMII/RGMII interfaces and with off-the-shelf network processor units (NPUs) or SONET mappers via a standard SPI-4.2 interface.
To enable full utilisation of shared hardware, including network processor units (NPUs), backplanes and switch fabrics, Harrier's intelligent oversubscription logic optimizes existing network infrastructure by eliminating unused bandwidth at the media access controller (MAC) layer.
Harrier implements 2:1 intelligent hardware oversubscription by aggregating 24 incoming Gigabit Ethernet ports to a single 10 Gbps NPU.
Implementing this hardware-based oversubscription in the router or switch reduces system cost per user by up to 40 percent without affecting network performance.
Taking oversubscription to a higher level, such as 4:1 or 8:1, enables further network cost reductions.
To ensure quality of service and bandwidth availability to all users, Harrier supports multiple priority queues per port and implements oversubscription algorithms based on Weighted Random Early Discard (WRED), Modified Deficit Round Robin (MDRR) and in-band PAUSE frame generation for flow control.
To simplify design complexity and reduce system cost, the device includes on-chip memory and utilises a Dynamic Memory Management system which supplies each port with a cache of virtual RAM efficiently allocating memory to users on an as needed basis.
The primary application for Harrier is in modular, high-density IP-based Ethernet LAN switch and router systems. As traffic enters the Harrier-based line card on a switch/router, it is pre-processed and rate-limited so that the NPU and switch fabric can be fully utilised.
In this implementation, 24 incoming Gigabit Ethernet ports can be processed by a single 10Gbps NPU. Harrier will dynamically handle bursts of traffic across these 24 ports and map the traffic onto a 10Gbps interface.
This allows a single 10Gbps NPU to handle 24 Gigabits of traffic, which results in more than a two-fold reduction in NPU and switching hardware requirements.
For metropolitan network applications, Harrier provides high-density, ultra efficient Ethernet over SONET aggregation. In this application, Harrier is connected to a virtual concatenation SONET mapper with GFP support.
Virtual Concatenation and GFP mapping have been developed to efficiently transport Ethernet over SONET metropolitan networks. SONET payload envelopes can be efficiently sized to match Ethernet services transports at 10/100/1000 Mbps increments.
By introducing intelligent oversubscription, operating in conjunction with virtual concatenation, carriers can take this mapping efficiency even further.
With Harrier, SONET payload envelopes can be sized to match the actual bandwidth utilized within standard Ethernet links, supporting more customers at a lower cost per customer.
Each member of the Harrier product family is a low-power 31mm x 31mm flip chip BGA device, making it extremely attractive for high-density network line card development where space and power availability are at a premium.
Its virtual on-chip RAM eliminates the need for external components, further reducing system cost, space and power requirements.
The Harrier devices come with a comprehensive, portable API that provides high-level access to internal registers and simplifies software development, and support extensive statistics for performance monitoring and billing.