Semiconductor design software specialist, Synopsys, has teamed up with Altera (distributed by Braemac )—a system-on-programmable-chip (SOPC) company—to provide what is claimed to be a unified solution for FPGAs, structured ASICs and ASICs.
The solution will be based around a range of Synopsys software products and Altera’s HardCopy device family and associated design tools. The collaboration should help accelerate HardCopy device implementations by optimising back-end design flow and providing customers access to expert Synopsys physical design resources that will complement Altera’s existing HardCopy design centre.
Additionally, designers can now use Synopsys’ Galaxy design platform front-end flow to design Altera Stratix FPGAs. This agreement is said to build on work already in progress for the development of a new timing-driven HardCopy back-end design flow based on Galaxy and optimised for Altera’s FPGA-to-HardCopy migrations. It is claimed that Altera and Synopsys will use the flow to further optimise the chip performance and reduce the turnaround time of HardCopy implementations.