Programmable logic vendors like to send Electronics News information about their latest multi-million gate field programmable gate arrays (FPGAs). These devices are impressive slices of silicon, often including embedded processors, memory, DSPs and high speed interfaces. And, in truth, we like to write about them. But the reality is that in Australia the devices are likely to be used by a handful of users at most, and the real market for programmable logic here is for more modest (and therefore less expensive) devices.
One approach to lowering the price of high-end architectures is to “remove” embedded elements (such as processors) from the die, and consequently remove the need for documentation and design support. The irony is that these features still reside on the chip, but the designer can’t access them. Other cost saving techniques employed by manufacturers include using a limited range of low cost packaging, and manufacturing at an older process node, for example 130-nm instead of 90-nm. This helps to maximise yield and push down manufacturing cost, allowing the vendor to sell to the customer at a cheaper price while protecting margins.
The two biggest suppliers in programmable logic, Altera (distributed by Braemac ) and Xilinx (Insight Electronics ) have both adopted this approach with variants of their Apex and Virtex chips respectively, to provide price-sensitive products without too much product development time. There is a limit to how much cost the supplier can strip out of a high-end device, however, and perhaps a better alternative for the mainstream market is to design “from the ground up” with economy in mind.
This thought has also occurred to both Altera and Xilinx resulting in families of programmable logic specifically designed to meet a low price point.
Price-focused programmable devices
Xilinx’s purpose-designed, low cost offering is the Spartan-IIE series. For the record, the Spartans inhabited a seventh and eighth century Greek city-state, best known for its adherence to a military lifestyle of discipline, endurance and simplicity. This is probably not a bad parallel to draw with a low-cost FPGA destined to spend its life in charge of a 24-hour industrial process.
Although the Spartan-IIE series has been around for four years, the latest extension to the family was introduced by Xilinx only in November last year. Offering 60 percent greater I/O and 125 percent more logic resources, the latest devices are said to enhance the existing Spartan-IIE family that now ranges from 50,000 to 600,000 gates.
The company says that the new chips are designed to offer customers a low-cost programmable device, but with a high I/O count. It claims that at up to 514 pins, Spartan-IIE chips “deliver the industry’s lowest cost per pin, and most comprehensive programmable I/O support”.
The additions to the family are the XC2S400E (400,000 system gates and 410 I/Os) and XC2S600E (600,000 system gates and 514 I/Os) devices, that are said to integrate more functionality into smaller form factors. “Based upon market research, we know that devices with up to 304 pins serve approximately 41 percent of the total ASIC market,” explains Clay Johnson, vice president and general manager of the General Products Division at Xilinx. “The Spartan-IIE extension products, extend the available market served by Xilinx to 65 percent of total ASIC shipments - a nearly 60 percent increase in the served available market for the Spartan-IIE family.”
Altera’s low-cost offering is called Cyclone. The company’s focus with this product is on lower densities, lower speeds, and a more restricted set of features than that of the high-end Stratix family. Altera manufactures the product on a detuned and one-metal-layer reduced variant of its higher-end architecture 130 nm copper process, courtesy of Taiwan Semiconductor Manufacturing Corporation.
The Cyclone logic-cell structure appears to synthesis tools similar to the cell of other Altera FPGAs. But internal optimisations have made it 30% smaller than the Stratix logic cell. Cyclone comes with a lower memory-to-logic ratio than Stratix, and the embedded memory runs at lower speeds (estimated at 200 MHz maximum). Cyclone FPGAs come with a maximum of two phase-locked-loops (PLLs). The I/O buffers focus on single-ended protocols, such as 66-MHz PCI, and don’t include Stratix’s integrated termination resistors, though they do comprehend some differential-signalling schemes at speeds as high as 311 Mbit/s.
It seems that Altera has stripped-out a lot out of Cyclone compared to Stratix. This is true, but the result is an extremely competitive price. Altera estimates this to be less than half the published prices of even the most aggressive competitor and which reflect an average 60% smaller die than that of a similar-logic-density Stratix device. Cyclone-based designs run on average much faster than earlier generation Acex 1K counterparts, and are available now(1).
What about the software?(2)
Experienced designers will point out that the cost of the silicon is only a small part of the project cost; it’s the price of the development software that can be the real killer. But, with a little bit of searching, it is possible to find bargain-basement versions of programmable logic suppliers’ design suites - albeit typically supporting a subset of product families and devices with a restricted set of functions. Altera’s freely downloadable Quartus II Web Edition software (version 2.2), for example, focuses its attention on mainstream Max 3000 and Max 7000 CPLDs and Acex, Cyclone, and Flex 6000 FPGAs, and it works with only one or a few devices in higher end FPGA families. It supports schematic- and text-based design entry, Verilog and VHDL synthesis, functional simulation and timing analysis, placement and routing and device programming through ByteBlaster, ByteBlasterMV, and MasterBlaster cables.
Xilinx’s counterpart to Altera’s freeware comes as the free ISE WebPack and WebFitter. ISE WebPack is conceptually similar to Atera’s Quartus II Web Edition; it supports a subset of Xilinx’s product line, and technical support services are available only through Xilinx’s Web site. ISE WebPack neither interacts with the Core Generator and FPGA Editor tools nor comprehends ChipScope Pro design verification. Unlike Quartus II Web Edition, ISE WebPack allows not only Verilog and VHDL design entry, but also Abel language synthesis.
All ISE variants interface with the optional free Mentor Graphics-developed ModelSim Xilinx Edition simulator, and other freeware ISE WebPack add-ons include the HDL Bencher automatic testbench generator, the StateCAD automatic state-machine-design generator, the ChipView prefit and postfit graphical utility to assign and view pin and logic placement, and the Xpower graphical power-analysis tool. Spreadsheet- and Web-based power-analysis tools are also available from Xilinx.
Whereas ISE WebPack runs only under Windows operating systems, WebFitter’s Web-based interface also supports Unix and other browser-compatible operating systems. The focus with this tool is exclusively on Xilinx’s CPLDs. It provides easy access to reports, notes, and device-price quotes. WebFitter enables design conversion from other tools and other manufacturers’ devices.
And the development kits?
Supplementing the lower-cost chips and freeware comes low priced development kits. Altera offers the Max 7000 Quick Start development Kit. It includes an evaluation board containing an EPM7128, four multiplexed, seven-segment LED displays, a power LED, test points, a clock oscillator, pushbutton switches and expansion headers. It also includes a ByteBlasterMV download cable and a Quick Start guide, a 6-V power supply, design software and documentation.
Xilinx based its Cool-Runner-II design kit on the XC2C256 (The company states that this kit is free “to qualified customers through the Xilinx worldwide distributor base”.) It includes an additional pad for a CoolRunner-II or XC9500 CPLD in a 44-lead VQFP.
Perhaps an expensive, comprehensive piece of hardware is overkill for your needs; schematics and Gerber files, HDL and software source code, and other reference materials for a validated and easily customisable design may be sufficient. The good news is that nearly all the programmable vendors’ websites contain freely downloadable material that will be of assistance. Xilinx’s resources are perhaps the best organised at the moment; the Emerging Standards and Protocols (ESP) section of the vendor’s website contains information categorised by various applications, such as automotive telematics, digital video and networking. You’ll also find reference designs within each product family’s collateral listing; Xilinx’s competitors’ sites also categorise information by application and product family.