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Power puts Moore’s Law in danger

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The often asked question “Is Moore’s Law slowing down?” once again was received a “no” at the Silicon Design Chain breakfast at the Design Automation Conference (DAC) in the US.

Edward Wan, senior director of design services marketing at Taiwan foundry TSMC, did say, however, that the tried and true semiconductor commandment is in danger and will suffer serious consequence if power management is not better addressed at the 90-nm node.

“Moore’s Law may not be slowing down, but the benefit of Moore’s Law is threatened by the industry’s ability to solve the power issue. It is clear to us that collaboration is a key to finding a solution,” Wan says.

Behind the issues with power are mobile devices that crave longer battery life, stationary devices that require reduced cooling requirements and applications that look to increase performance by lowering power. Basic physics and the complexity of designs has also put pressure on power, Wan noted.

The TSMC director spoke on behalf of the foundry on the final day of DAC, accompanied by executives from Cadence, ARM (distributed by Bluewater Systems ) and its physical IP branch Artisan, and Applied Materials, about a test chip the team of Silicon Design Chain companies have developed. When tested, the chip shows 37.9 percent savings in dynamic power and 46.7 percent savings in power leakage.

Aurangzeb Khan, a Cadence VP, tipped off the technology, but gave little detail at that time.

This breakfast featured an example, a test chip based on the ARM1136JS RTL, GDSII, Cadence’s Encounter platform, and Artisan SAGE-X libraries and memory compliers, and runs on a TSMC 90nm process.

The chip uses such techniques as voltage islands, clock gating, reduced Vdd and threshold voltage option to help tackle the power.

“From our perspective at TSMC, there is no sign of slowing down, in neither the technology development nor the technology introductions. Although Moore’s Law continues, we do see a potential slowdown in the adoption of the advanced technologies because there are worries about higher design barriers – not just technical, but financial barriers,” Wan says.

“In order to come up with an effective low power solution, we have to integrate process technology, transistor devices, libraries, design methodology, the tools, the test chip design and the test chip fabrication. This is where the collaboration between Cadence, ARM, Applied and TSMC comes in,” he concludes. “No one party can do it alone.”

Wan said that in accordance with Moore’s Law, TSMC has introduced a major process node every one-and-a-half to two years. At the 90-nm node, the company claimed to see a 25 percent quarter-over-quarter defect density reduction. Wan further said TSMC expects about 10 percent of its revenue to come from 90-nm products this year.

The Silicon Design Chain chip is in production now and, according to Wan, will see more than 100 product tapeouts by year’s end.

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