DALLAS Semiconductor, represented in Australia by Arrow Electronics , has released the MAXQ architecture, combining quiet operation with a 16-bit RISC architecture. The one-cycle MAXQ RISC architecture combines good clock use with intelligent clock distribution.
When integrating analogue circuitry with digital blocks, the operating environment must be kept as noise-free as possible. Clocking and switching occurring in the digital circuits of a microcontroller core inject noise into the sensitive analogue circuitry. The challenge is to maximise microcontroller performance while minimising clock noise that may adversely affect analogue circuits.
The MAXQ architecture increases the microcontroller performance through improved clock-cycle efficiency, minimising clock cycles required to execute a task. It also takes advantage of a Harvard-style memory map to allow simultaneous program and data memory access, eliminating the clock-cycle inefficiencies of sharing a bus.
The MAXQ does not implement an instruction pipeline to support its one-cycle operation. Instruction fetch, decode, and execution occur in the same clock cycle. This eliminates clock cycles normally wasted when program branching occurs. Since nearly every instruction mnemonic is performed in one clock cycle, the MAXQ's performance approaches 1MIPS per MHz.
Digital operations in the MAXQ core are performed on the positive edge of the system clock, leaving a virtually noise-free falling edge ideal for performing analogue functions. Clock gating is used to further reduce clock noise and power dissipation.
The MAXQ instruction set is composed of 33 C-friendly instruction mnemonics, each of which translates into a simple move operation between two functional modules. Knowing exactly which functional modules are involved in the move operation allows highly targeted, per-instruction clock gating. It is aimed at medical, automotive, metering, consumer and industrial automation equipment.