ALTIUM has expanded the HDL capabilities of its Nexar FPGA-based digital design system with the introduction of support for Verilog. Service Pack 2 for Altium's DXP 2004 design systems includes updates for Nexar and the Protel board-level design system.
It adds syntax-aware code editing, parsing and compilation support for Verilog to Altium's design capture system. This will allow engineers to use any combination of block diagram, VHDL and Verilog to capture circuit hardware for FPGA implementation.
Engineers wishing to process Verilog designs through HDL simulation and synthesis will need third-party simulation and synthesis engines, as the inbuilt DXP 2004 engines currently support VHDL only. This can be done within the DXP platform, which provides transparent interfacing with the ModelSim and ActiveHDL simulators and Synplicity, Xilinx XST and Altera Quartus synthesis engines. When an external engine is selected, full Verilog design flows can be carried out within the DXP 2004 environment. Altium plans to upgrade its DXP synthesis and simulation engines with full Verilog support in subsequent service packs.
The addition of Verilog support to Nexar will expand the design system's reach into existing FPGA markets and allow all FPGA designers access to Nexar's environment for FPGA-based systems development. Nexar allows the interactive development of complete systems, including processor-based designs, on an FPGA platform. The Nexar design methodology - LiveDesign - enables real-time communication with active devices in the circuit, such as processor cores and virtual instruments, that are running inside the target FPGA. Nexar allows interactive, live development and debugging of systems without the need for simulation at the system level, significantly reducing system development time.