Home > Tough future for EDA

Tough future for EDA

Supplier News

Electronics Design Automation (EDA) is a niche sector solving some of electronics’ biggest design problems. It is where academia meets the electronics engineering real world. Where PhDs are needed to ensure next generation electronics products and applications continue to become smaller, faster, cheaper, lower power, more intelligent, ubiquitous and pervasive.

EDA is blazing the trail to 130, 90, 65 and even 45-nm silicon geometries that allow continued adherence to Moore’s Law. If EDA falters, progress in the rest of the electronics industry falters. But EDA can’t continue to succeed in its current form.

This article will look at some of the key issues in EDA today. It draws heavily on the recent DATE 2005 conference and exhibition in Munich, Germany—Europe’s largest EDA event (with 4800 visitors). Just under half the visitors were design engineers and one in five came from academia—reflecting the ever increasing commercial/academic mix required to solve EDA’s technical challenges. Exhibitors included Australian-born EDA firm VaST Systems Technology that although now registered in the US, has half its workforce in Sydney.

In addition, Electronics News sought the opinion of Australian-owned, Sydney-based Altium, which exhibited at the Embedded World 2005 show at Nuremberg, Germany, just prior to DATE.

Design tools struggle

EDA centres on improving the software and hardware design flows of System-on-Chip (SoC), ASIC/ASSP (Application Specific Standard Product), FPGA, IP and analogue design, and systems based on them. The market is dominated by three giants – Cadence Design Systems, Mentor Graphics and Synopsis. However, a significant amount of leading-edge innovation within EDA comes from the small to medium-sized players (that are often later acquired by one of the big three). Naturally, these innovative products are designed to be used alongside or in conjunction with Cadence, Mentor and Synopsis design platforms and products to further enhance their scope.

“Design complexity is growing exponentially,” says Lauro Rizzatti of EDA emulation and verification firm EVE. “The leading edge of the SoC industry is fast approaching devices with [a billion] transistors. This complexity is out-growing the capabilities of traditional design tools. In addition—at 130 nm—the proportion of relative design effort in embedded software required to bring a device to market overtakes hardware, and will further dominate at 90 nm and beyond.

“At the same time, at 90-nm one re-spin typically costs around [$2 million] and that’s before factoring in that for fast moving markets [for example, consumer] a three month re-spin induced delay can result in a 25 percent loss in revenue,” Rizzatti explains.

“You really want to avoid mistakes in both hardware and software and in particular the integration between them, well ahead of first silicon.”

EVE’s ZeBu hardware-assisted FPGA-based verification platform is said to meet this need. It is claimed to be faster and more affordable than traditional emulation systems while offering higher capacity and better hardware debugging than conventional FPGA prototyping systems.

Given that some estimates for 90 nm SoC projects say the average re-spin count is three per design, “right first time silicon” within the time and cost constraints of a typical design cycle is the Holy Grail of EDA. Numerous vendors approach this objective innovative ways. (Also see sidebar Best of DATE.)

130-nm and beyond

Moore’s Law—roughly translating to the number of transistors on a piece of silicon doubling every couple of years—has proved remarkably resilient over the past 40 years. But enhancing transistor performance simply through device miniaturisation is becoming increasingly difficult—both technically and economically—and is demanding a major re-think of design methodology.

“At 130 nm, industry trends started to veer off long term classical trends and began failing to meet targets,” explains Garry Hughes, VP, ASIC and Foundry Solutions at IBM’s Systems and Technology Group in the US. “Gate oxides are now getting so thin that you are looking at single digit atom gate oxide thicknesses where being off by a single atom means being off by a significant proportion. Solving these problems will rely on tighter linkage between process technology, design tools, device models and model correlation. And all of these solutions will need to fit together in an end-to-end design methodology. Point tools, point products, point solutions won’t work – all tools will need to work together in an end-to-end design ecosystem.

“What we are finding is that no single company or vendor does everything the best. No single company can design all the IP it needs by itself – nor would it want to. And this stuff is getting so hard that most companies won’t have the engineering teams within their own company to take on these challenges alone.”

The view is echoed by Steven Schulz, President and CEO of the not-for-profit Silicon Integration Initiative Inc (Si2, www.si2.org), a worldwide consortium of semiconductor and EDA companies that collaborate to promote interoperability of design tools and flows: “The problems at 90 nm are much bigger than any one vendor can attack on its own. Indeed successful semiconductor fabrication at 90 nm and below cannot occur unless designs are built to be manufactured and manufacturing processes are built to encourage right first time silicon. Si2 aims to influence this change at industry level by bringing together the major players.”

This includes an OpenAccess initiative that defines an application programming interface (API) and semantic data model that EDA applications and vendor tools can use to interoperate with each other.

The technical issues are numerous. Timing, for instance, is proving particularly problematic. The larger the number of gates and transistors – the more difficult it becomes to make them all switch at the same time (in other words skew is increased). Garry Hughes says advanced statistical timing analysis will be required to move beyond the “best best” and “worst worst” traditional ASIC timing approaches that are now becoming too risky.

Power leakage is another well documented problem. “Active power leakage used to dominate, now standby power is just as big a contributing factor,” continues Hughes. “We have effectively got to the point with CMOS that everything leaks almost like it was a bipolar circuit. One way to deal with this is voltage islands that although sound simple in practice demand a lot of logic to route everything properly.”

Noise is another major issue – the smaller the circuit operating voltage the bigger the impact of noise on performance.

One company attacking power issues at 130 nm and below is Apache Design Solutions with its RedHawk, NSPICE and SkyHawk products. The company estimates that around 60 percent of its customers initially approach them because their product is not working properly due to a power failure issue. The problem tends to affect the whole chip and can only be solved using accurate and comprehensive noise integrity solutions early in the design cycle.

Finally, the luxury of being able to design a chip and then a package will vanish. They will essentially have to be designed together and EDA design methodology will have to expand to encompass this.

Opening EDA to a wider audience

These factors are not helping to ease the legendary complexity of EDA. This creates a “barrier to entry” that can limit accessibility to the wider electronics design community, with the very real risk of creating barriers to innovation that may prove crucial in solving some of the major issues.

One company working to lower these barriers is Sydney-based Altium.

Altium has long championed the vision of providing every design engineer with easy access to state-of-the-art design tools and we have had notable success in making EDA accessible to a wider electronics design audience,” says the company’s European regional director, Klaus Pontius.

Pontius supports this statement by referring to the company’s latest flagship Nexar product that is said to be the electronics design industry’s “first comprehensive, vendor-independent system for designing embedded systems on an FPGA platform”.

Altium claims that unlike other tools on the market, Nexar does not require engineers to have to acquire Hardware Description Language (HDL) and RTL experience in order to put systems onto an FPGA. Instead it uses familiar board-level design methodologies to implement complete system-level applications within programmable chips, making the potential of FPGA-based, embedded systems design accessible to mainstream engineers.

“Basically by being able to run real software on real hardware in real time you don’t need any kind of emulation – you’re always working with the real product on an FPGA,” summarises Pontius.

Convergence impacts EDA

One of the biggest drivers is digital convergence especially in mobile devices destined to become personal communications hubs demanding unprecedented levels of semiconductor integration. They will also need to offer hundreds of times better performance and power conservation than, for example, current mobile phone designs.

“This can only be achieved by scaling, which is the number one challenge for achieving future digital convergence,” says Jeong-Taek Kong, VP of Corporate Computer-Aided Engineering within Samsung Electronics’ Semiconductor Business Unit in Korea.

Current semiconductor scaling is forecast to continue down to about 22 nm in 2016 (see public.itrs.net).

“But it is extremely difficult and challenging – even at 60 and 45 nm,” continues Kong. “As scaling continues, the cost per transistor will decrease exponentially in the long term. But in the short term achieving scaling will be expensive in design costs [particularly software], allied with the challenge of meeting consumer product life cycles already as short as 6 months.”

Kong says the challenge will be met in two ways. Technically it will centre around increasing design productivity, reducing power consumption and improving manufacturability and yield. Commercially it will demand a paradigm shift to justify the high semiconductor [and R&D] costs needed to create killer applications. Collaboration within the industry will be key to share the costs but it will demand bridging cultural, political and even geographical differences in the name of market-driven rather than technology-driven SoC design.

A further application discussed at DATE 2005 was biochips. “Biotechnology and life sciences may trigger a revolution over the next 50 years comparable to the impact of microelectronics,” predicted Dr. Roland Thewes, head of Biochip Research at Infineon Technologies. “Currently this centres around being able to measure DNA sequences in a pre-defined sample for the purposes of general research, drug development and medical diagnosis.”

EDA will be indispensable for coping with the ever increasing design complexity of successfully implementing giga-gate, nanoscale designs in silicon.

However, what designers want is end-to-end, structured solutions that simplify as much of the complexity as possible without compromising conventional design flow efficiencies and cycle times.

They will look to EDA to provide this solution – even if the EDA industry itself has to substantially reorganise and re-think existing business models in order to meet the demand.

Best of DATE

VaST Systems Technology provides tools and models for electronic system level (ESL) SoC and real-time embedded software development. VaST’s architectural-driven design solutions allow users to create a virtual system prototype in software that becomes the golden reference model for the concurrent development of hardware and software. At DATE it launched a peripheral device builder (PDB) that will allow customers of the company’s Comet and Meteor tools to develop peripheral devices such as interrupt controllers, DMA engines, timers, clocks and memory controllers.

TransEDA specialises in ready-to-use verification solutions that are designed to provide a full coverage but end-point defined verification process. “Verification tends to grow to expand to fill the time available,” says Worldwide Sales and Marketing Manager, Modesto Casas. “There is also a tendency to either over-test or simply keep testing until an end date and then stop. What designers really need is a reliable way to know when they have finished testing.”

Prosilog provides solutions for SoC design and verification – particularly IP integration and reuse. Its Magillem platform-based design environment offers a range of packaging and interconnection tools at the RTL (Register Transfer Language) and transaction level.

Celoxica offers a range of ESL, C-based design and synthesis tools that are said to target the broadest range of silicon architectures. They allow designers to generate low level digital circuits from high level system and behavioural descriptions. This includes enabling software algorithms implemented in microprocessor-only architectures to be re-targeted at silicon that is made up of both software and hardware.

Calypto focuses on bridging the gap between electronic system level design and IC implementation at the RTL level. Its tools are claimed to support faster verification times and design at higher levels of abstraction – in particular optimising RTL chip models for power and timing.

Jasper Design Automation delivers static block-level RTL design and verification solutions that are said to speed the development and lower the schedule risk for complex IC circuits. Its flagship JasperGold product exploits leading edge formal verification technology to exhaustively verify functional behaviours of RTL blocks without simulation or test vectors, enabling formal assertion-based verification.

Xpedion specialises in RF simulation in RFIC/wireless and high frequency SoC designs. It claims to provide transistor level frequency-domain simulation techniques for rapid and accurate analysis of analogue circuit behaviour without imposing constraints on circuit size, frequency or complexity. “The problem is that you can’t verify RF performance due to its chaotic mathematical behaviour,” says Pete Rodriguez, President and CEO. “But we have developed a way to simulate it to near verification levels and thus significantly reduce time-to-market.” The company’s GoldenGate Simulator can analyse circuits in the multi-GHz range including full transmitter/receiver chains, while its GoldenGate Model Compiler allows RF designers to safely distribute, analyse and use circuit IP built using popular tools such as the Cadence Composer Schematic Capture.

Newsletter sign-up

The latest products and news delivered to your inbox