ALTIUM ’S Service Pack 2 for the Nexar FPGA-based system design software will include a 32-bit, FPGA-based RISC processor that will simplify the development of 32-bit systems targeted for FPGA implementation.
The processor has been designed to minimise the complications associated with 32-bit system design. The TSK3000 RISC processor is based on the Harvard architecture, but features a simple memory structure and hardware-based vectored interrupt handling to make coding simpler. Interfacing with the processor is simplified by the provision of separate bus interfaces for connecting memories and peripherals. A user-configurable, fast on-chip memory system improves performance and simplifies memory system design.
The TSK3000 uses the open-standard Wishbone system-on-chip interconnect bus to allow system designs to be used on any target FPGA families without licensing issues. A selection of Wishbone peripherals is supplied with the Nexar design system.
The TSK3000 is supplied presynthesised for a wide variety of target devices. This means the device can be incorporated easily into a system design at the block level, eliminating the need to manually instantiate the core in HDL and simplifying the core's use in FPGA-based systems. It also enables the core to be used with any FPGA device of suitable capacity that is supported by the Nexar design system. This gives engineers a device and FPGA-vendor-independent, 32-bit system hardware platform.
Service Pack 2 for Nexar will also see the addition of full embedded software development support for the TSK3000, with a C compiler based on Altium's Tasking Viper compiler framework as well as a fully-integrated assembler, profiler and source-level debugger.
Altium's Nexar design software allows the interactive development of complete systems on an FPGA platform. LiveDesign is the Nexar design methodology. It allows real time communication with active devices in the circuit that are running inside the target FPGA. Nexar integrates with Altium's NanoBoard, an FPGA development board with swappable target devices and acts as a nano-level breadboard to allow interactive development and debugging of systems without the need for simulation at the system level. This can significantly shorten system development time.