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PC/104-Plus and PCI-104 boards from Allied Data Systems

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article image PC/104-Plus and PCI-104 board

Data Device Corporation (DDC), represented in Australia by Allied Data Systems , have introduced the new multi-protocol PC/104-Plus and PCI-104 boards (BU-65590Cx) that provide up to two dual redundant MIL-STD-1553 channels, sixteen ARINC 429 receive channels, eight ARINC 429 transmit channels, eight user-programmable Digital Discrete I/Os, eight user-programmable Avionics level (+35V) Discrete I/Os, an IRIG-B time synchronisation input and an IRIG-B time generator.

The card provides a unique solution for applications that require both MIL-STD-1553 and/or ARINC 429 interfaces and allows box manufacturers to save space and weight by combining multiple protocols on one card says Mike Hegarty, DDC’s MIL-STD-1553 Marketing Manager.

The card is available with DDC’s newly enhanced Software Development Kits (SDK) for MIL-STD-1553 and ARINC 429 data bus applications.

The SDKs allow users to develop ‘C’ source code to simulate, monitor, or troubleshoot 1553 and/or 429 data buses simultaneously or independently with support for the latest operating system versions including VxWorks 6, Linux 2.6, and Windows 2000/XP.

These SDKs allow users to quickly integrate DDC’s multi-protocol avionics card into ‘C’ code applications. A common SDK exists across all operating systems allowing the programmer portability across multiple embedded and test platforms. The easy-to-use high-level functions abstract all low-level hardware accesses and memory allocation such that specific hardware knowledge is not required.

Each 1553 channel supports new standard features such as 1 MB RAM with parity per channel, 48-bit/1µs or 100nS time tag and built-in self-test. An intelligent hardware offload engine provides extremely low PCI bus and host CPU utilisation while storing 1553 Monitor data in a convenient IRIG-106 Chapter 10 format.

The IRIG-106 Chapter 10 format is commonly used for digital flight data recorders. Each ARINC 429 channel supports high/low speed operation, message scheduling, label filtering and full error detection.

Received data can be stored in either FIFO buffers or system address label mailboxes. Transmit data can be sent in FIFO mode or scheduled rate mode on each transmit channel.

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