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MIL-STD-1553 PMC board from Allied Data Systems

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article image MIL-STD-1553 PMC board

Data Device Corporation (DDC), represented in Australia by Allied Data Systems , have introduced a new MIL-STD-1553 PMC board (BU-65578F/Mx) that provides up to eight dual redundant MIL-STD-1553 channels, eight user-programmable Digital Discrete I/Os, eight user-programmable Avionics level (+35V) Discrete I/Os, an IRIG-B time synchronisation input and an IRIG-B time generator.

The card can be ordered with either rear or front panel I/O and is available for convection or conduction cooled applications.

DDC’s new Extended Enhanced Mini-ACE (E²MA) Architecture is utilised for the 1553 interface. An evolution of DDC’s Enhanced Mini-ACE Architecture, the new E²MA architecture builds upon previous generations of DDC products while maintaining full API compatibility.

Each 1553 channel supports new standard features such as 1 MB RAM with parity per channel, 48-bit/1µs or 100nS time tag and built-in self-test.

An intelligent hardware offload engine provides low PCI bus and host CPU utilisation while storing 1553 Monitor data in a convenient IRIG-106 Chapter 10 format. The IRIG-106 Chapter 10 format is commonly used for digital flight data recorders.

The card’s high channel count saves PMC sites allowing for smaller and lighter systems as well as lower power consumption per channel says Mike Hegarty, DDC’s MIL-STD-1553 Marketing Manager.

The card includes DDC’s MIL-STD-1553 Plus ‘C’ Software Development Kit (SDK), which allows users to develop ‘C’ source code to simulate, monitor, or troubleshoot 1553 data buses with support for the latest operating system versions including VxWorks 6, Linux 2.6, and Windows 2000/XP. This SDK enables users to quickly integrate DDC’s Eight Channel 1553 PMC into ‘C’ code applications.

A common SDK exists across all operating systems allowing the programmer portability across multiple embedded and test platforms. The easy-to-use high-level functions abstract all low-level hardware accesses and memory allocation such that specific hardware knowledge is not required.

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