Beginning in the 1980s, design teams used logic analysers extensively to debug embedded systems containing high-performance processors. Development teams designed in PCB connectors with a pre-specified layout for tracing the processor. For 32-bit processors, this requirement typically included 102 to 136 signals consisting of the data, address and status signals. Logic analysers still require a certain arrangement of these signals to be laid out on the user’s target system. Each processor has an associated logic analysis configuration file and inverse assembler that works with a specified PCB layout. Inverse assembly software converts the acquired data to instruction mnemonics. Processor execution trace measurements are available as long as teams plan for debug early in development.
In the late 1990’s 32-bit embedded processors began incorporating technologies that made it more difficult to make logic analysis trace measurements. Shrinking real estate available for debug made it impractical for a number of designers to include connectors for tracing. Even if the design team had designed in connectors for trace measurement, if the processor was executing out of cache memory, no signals of relevance would be transmitted to the pins which the logic analyser was monitoring. Turning off cache caused the system to run at a slower rate and could mask problems that would only occur at real system speeds. In addition, pipelining and out-of-order execution made it more difficult for logic analysis vendors to unravel information on the bus.
Recently, Agilent and Xilinx (distributed by ) collaborated to develop a logic analysis trace solution for the latter’s MicroBlaze processor core—residing on its Virtex and Spartan FPGAs—that overcomes the traditional difficulties of tracing software execution using a logic analyser. The solution contains two essential building blocks: An inverse assembler for MicroBlaze, and MicroBlaze Trace Core (MTC).
MicroBlaze inverse assembly
For PCB layout, design teams enable the inverse assembler by routing MicroBlaze program counter signals (PC_Ex) and the valid cycle signal (Valid_Instr) to pins. Routing these signals to a specified layout allows for fast connection to a logic analyser via mictor, samtec, or softtouch probing. Or, a user can connect the logic analyser to these signals using a berg strip or header using individual flying leads. Due to their reprogrammable nature, FPGAs with MicroBlaze can be traced late in the development cycle. As long as a sufficient number pins have been reserved for debug, designers can reconfigure their FPGA for MicroBlaze tracing without any PCB changes.
The Agilent inverse assembler for MicroBlaze reconstructs program flow by capturing the instruction address of each executed instruction and looking up the associated opcode in the object module format (OMF) file. It then decodes the opcode into a MicroBlaze mnemonic.
As pins available for debug are often scarce, the inverse assembler includes a capability that reduces the number of required pins. Although there are 32 PC_Ex signals, the number of external signals needed for capturing a logic analysis trace is typically significantly less than 32. This reduction is accomplished using two different techniques. First, the upper address bits do not need to be traced. For any given design, a certain number of upper address bits are static. Pin reduction can be achieved with 1 additional pin decreased for each static upper address bit in the program counter. This information is specified by the use. Also, the lower two address bits do not need to be traced. All instructions start on 4-Byte boundaries. Using these techniques, tracing a program size of 1 MByte requires only about 18 pins.
Unlike standalone processors where logic analysis tracing becomes impossible when cache is enabled, a logic analyser can trace MicroBlaze even when cache is enabled. This is a result of being able to program the FPGA to bring out signals at the execution stage of the MicroBlaze pipeline.
Agilent logic analysers come standard with a source correlation window. By reading a symbol file (.elf format), the logic analyser can associate captured addresses with the high level software associated with that address. Opcode images are found in the text sections of the elf object files. As the user steps through assembly instructions, the equivalent line in the source code for this instruction is also highlighted. Or, the user can step through high-level source code while the logic analyser simultaneously displays the associated instruction mnemonics in the lower window. The user can right-click in the source code to set up the logic analysis trigger (trace specification) for the next acquisition.
MicroBlaze trace core (MTC)
An optional MicroBlaze trace core (MTC), reduces the amount of time and the number of pins required to trace MicroBlaze with a logic analyser as shown in Figure 1. The MTC core, co-developed by Agilent and Xilinx, works exclusively with the Embedded Developer Kit (EDK) flow. Design team members can graphically add an MTC core to their design. Core parameters include pin compression using TDM, pin location and I/O standard.
The MTC core provides four key values:
First, the MTC core connects required MicroBlaze signals to pins (pre-synthesis).
Second, the core incorporates time division multiplexing to reduce the number of pins required by a factor of 2. Two MicroBlaze signals are time division multiplexed onto a single pin with data valid on the rising edge of the clock for signal one and data valid for signal two on the falling edge of the clock. A demux clocking mode in the logic analyser decompresses the information and splits it into 2 separate logic analysis channels.
The MTC core includes technology that reduces initial set-up time from hours to seconds and eliminates manual errors that can happen during the PCB layout. Tracing MicroBlaze can be done late in product development as the MTC core eliminates the need to layout a PCB with a specific MicroBlaze signal pattern for mictor, samtec, or softtouch probes. Via JTAG, the logic analyser sends an autosetup message to the MTC core. The core outputs a training pattern on a specific MTC pin. The logic analyser looks for this training pattern across its channels and discovers which channel is connected to the MTC pin. The logic analyser knows how each MTC core input is routed through the core to pins from its communication with the MTC core. Using this correlation, the instrument now has sufficient knowledge to determine how to set up the physical connection between specific microprocessor signals and the specific input channel on the logic analyser. This process is sequentially repeated for each MTC output pin.
The MTC core, constructed entirely of flops and LUTs, uses a multi-stage pipeline (typically 4) to minimise impact on device timing when the core is inserted as shown in Figure 2. MTC cores are very small. An MTC core in a XC2V3000 device consumes roughly 1 percent of the LUTs and flops.
FPGAs enable fast accurate processor execution tracing not available in stand-alone processors. Agilent’s inverse assembler for MicroBlaze soft processor core provides design teams with an effective tool for tracing software flow. Agilent’s royalty-free MTC core, distributed as part of EDK (beginning with Version 8.1), minimises the time to set-up the measurement and eliminates the need for a specified PCB layout.
Further information: Joel Woodward works for Agilent Technologies.