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SOC high speed test solution

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AGILENT Technologies has released an automated test solution for high-speed system on a chip (SOC) devices. It is part of the Agilent 93000 SOC series. It enables functional testing of high-pin-count devices up to speeds of 3.6Gb/s.

It uses by Agilent’s Pin Scale 3600 digital card, which offers per-pin scaleability from 800Mb/s to 3.6Gb/s, allowing the test system to be configured to match device requirements, pin by pin and at a low cost.

High-speed SOC devices are widely used in computer, digital consumer, communications and networking products. The miniaturisation of consumer electronics is causing SOCs to becoming very complex. The uncertainty in the rate of integration and the convergence of consumer devices requires that test equipment be able to test next-generation SOCs with higher speeds and more interfaces.

Next-generation SOCs are designed using deep submicron processes that generate a new class of defects and require faster, more accurate testing. Nanometer fabrication defects such as timing failures manifest themselves only at higher frequencies and must be tested at speed. Signal integrity issues such as inductive crosstalk and electromigration cannot be revealed by current simulation techniques and need to be identified by using at speed functional tests.

The Pin Scale 3600 digital card allows each test pin to be configured from 800Mb/s to 3.6Gb/s using software upgrades that can be performed instantly to meet changing test needs. Each pin offers both single-ended and differential I/O test capabilities that make it possible to test a wide range of interfaces including DDR, G-DDR, PCI Express, S-ATA, HyperTransport and Front Side Bus (FSB). Automated test equipment can be matched to the device through software scaling, pin by pin, which results in lower costs.

The Agilent Pin Scale 3600 digital card has a test processor per-pin architecture, which localises all test processing instead of using centralised resources. This results in minimal measurement overhead and higher throughput. This architecture also delivers a differential pin edge placement accuracy (EPA) of better than ±30ps, which is required for high-speed device testing.

The 93000 SOC has up to eight independent clock domains and can satisfy the most complex timing needs for concurrent at speed testing of multiple buses running at non-friendly speed ratios (bus fractions). As the speed of next-generation interfaces rises above 3.6Gb/s it will allow customers to upgrade to more than 8Gb/s functional test capabilities.

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