Agilent , Tyco Electronics, Texas Instruments, Intel , Cadence, Gennum, Marvell, Mindspeed and Velio Communications have united to formulate an interoperable standard for high-speed backplanes.
The high speed backplane initiative (HSBI), which also counts another 28 companies as contributors, will create an interoperable solution for higher speed backplanes by addressing issues associated with electrical signalling and protocol, according to Tyco Electronics semiconductor relations manager and HSBI secretary John D’Ambrosia.
“The HSBI is an exciting industry effort because it will provide a serialiser/deserialiser (SERDES) roadmap for all other standards bodies,” D’Ambrosia said.
D’Ambrosia said the purpose of the group is to develop a serial link technology capable of sending data at rates of 4.976 to 6.375Gbps across a backplane environment up to a distance of 30 inches including two connectors.
Future work will address 10Gbps and higher data rates over the backplane.
The developed specifications will define basic I/O levels and performance levels achieved when interfacing to the backplane environment.
To address multi-protocol support, the HSBI will develop specifications for 8B10B, SONET/SDH, and 64B66B encoding schemes, so that they may be carried over an HSBI link, according to Force10 Networks chief scientist Joel Goergen.
“With the efforts of the HSBI to ensure high-speed SERDES interoperability, systems vendors can meet their growing backplane bandwidth demands with multi-sourced parts that deliver 6 to 10Gbps speeds,” Goergen said.
“Interoperability between the devices is essential to create an environment where parts vendors continually improve their products with respect to cost, power and receiver sensitivity – things that are essential for the systems vendors to remain competitive.”
The HSBI initiative also provides an upgrade path for current CMOS-based 2.5/3.125Gbps backplane systems, the organisation added.
More information: http://www.hsbi.org/