AGILENT Technologies has announced a collaboration with CEA-Leti to define and implement a design flow for the development of next-generation wireless systems.
CEA-Leti, located in Grenoble, France, is a laboratory dedicated to microelectronics and microtechnologies research.
Agilent and CEA-Leti expect the wireless system design flow, based on Agilent's Advanced Design System (ADS) EDA software, to shorten design time, reduce risk and allow system designers to modify and reuse existing circuit intellectual property for advanced applications.
CEA-Leti is currently using ADS and the Agilent Ptolemy simulator to investigate and develop applications for fourth-generation (4G) wireless communication systems.
Today, the Ptolemy simulator has the capability to integrate MATLAB and C++ models.
In the first phase of the collaboration, Agilent's EEsof EDA division and CEA-Leti plan to focus on integrating the SystemC open-source class library into the ADS Ptolemy simulator. The results of this effort will be available in the next ADS release in 2006.
Agilent's ADS is an EDA software platform that supports system and RF design engineers developing designs from simple to the most complex, from RF/microwave modules to integrated MMICs for communications and aerospace/defense applications.
It has a complete set of simulation technologies, ranging from frequency- and time-domain circuit simulation to electromagnetic field simulation, allowing designers to fully characterise and optimise designs in a single, integrated design environment.
The Agilent Ptolemy simulator is a system-level simulation and design tool for ADS that is based on a hybrid of data flow and timed synchronous technologies.
It simplifies the design and simulation of digital- (DSP), analogue-, and mixed-signal-based RF systems and circuits, including wireless and wireline receivers, transmitters, modems, cellular phones and radar.
The integration of the SystemC open-source C++ class library and a methodology that can be used to create cycle-accurate models of software algorithms, hardware architecture, system-on-chip interface and system-level design is expected to allow system designers to specify front-end performance and validate hardware implementation.