Agilent Technologies have introduced SystemVue 2008, a new electronic design automation (EDA) platform for electronic system-level (ESL) design. The new platform cuts physical layer (PHY) design time in half for high-performance communications algorithms and system architectures, for both wireless and aerospace/defense applications.
The new SystemVue 2008 platform represents a new category of design tool from Agilent Technologies for system architects and algorithm developers.
SystemVue 2008 unifies the flow and creates a standard ESL toolset that is fast and easy to use. System designers finally have a place where they can innovate on both sides of the A/D converter, instead of overcoming limitations of tools that were never intended for their task.
The new Agilent SystemVue 2008 provides an easy-to-use environment with innovative simulator and modeling technologies, along with links to hardware implementation and test. It allows algorithm creation and prototyping for challenging communications system architectures at the physical layer.
SystemVue bridges an important design flow gap between algorithm developers and the mainstream design community and lowers the cost of ownership by unifying a disjointed flow at an affordable price. SystemVue complements existing general-purpose EDA tools used to design field-programmable gate arrays (FPGAs), digital signal processors (DSPs), application-specific integrated circuits (ASICs) and Analog/RF components.
SystemVue 2008 suits system architects of high-performance PHYs, and algorithm developers for emerging wireless PHYs, such as 3GPP LTE. Aerospace/defense applications, such as software-defined radio (SDR), satellite communications and radar will also benefit from SystemVue 2008.
Key features of Ailment’s SystemVue 2008 include:
- Dataflow simulator handles multirate and multicarrier signals with RF-true effects up to 10x faster than general-purpose simulators.
- RF architecture tools provide valuable analog insights.
- Richer set of accurate RF/Analog models allows effective system partitioning.
- Hundreds of extendable block libraries save time for communications, signal processing, RF, fixed-point and standards-compliant functions.
- Native polymorphism switches easily between language-based C++, m-code, Verilog/VHDL or GUI-based blocks, to work naturally with ESL design flows.
Native math language support:
- This feature maintains compatibility with existing algorithms and processes.
- It also supports creation, simulation, debugging, TCP/IP instrument connectivity and scripting.
- The environment is built for fast-turnaround communication system design with convenient verification.
- VHDL/Verilog generation includes support for FPGA rapid-prototyping.