Agilent Technologies Inc. launches the J-BERT N4903A, a high-performance serial BERT with a built-in, compliant and tuneable clock data recovery (CDR).
The International Engineering Consortium (IEC) acknowledges individuals and companies that offer innovative and unique applications, products, technologies and services of impact to the semiconductor industry.
The J-BERT N4903A built-in clock is the only complete jitter tolerance test solution. J-BERT N4903A provides integrated and calibrated jitter sources for stressed eye testing of gigabit receivers. The new compliant and tunenable CDR is also integrated into the J-BERT box.
This enables engineers in characterization and validation labs to get precise jitter budget results for clock-less devices. Engineers save test setup time by using J-BERT's new library of compliant CDR settings for many popular standards, such as PCI Express(r), Serial Advanced Technology Attachment (SATA), Fibre Channel, fully buffered DIMM, Common Electrical interface (CEI), 10 Gb Ethernet and XFP/XFI.