Agilent Technologies has introduced Integrated Verification Toolkit for signal integrity design.
Intended for use with Agilent's industry-leading Advanced Design System (ADS) EDA software platform, the new toolkit identifies and analyses sources of performance-degrading jitter in multi-Gigabit communication link designs.
It helps designers find and remove the causes of jitter before hardware prototyping begins, eliminating costly redesign later in the development cycle.
"The recent signal integrity breakthroughs we've made have expanded our RF and microwave EDA technologies into high-speed digital design," said Joe Civello, product marketing manager with Agilent's EEsof EDA division.
For the first time, designers of high data-rate interconnect and serial data links can perform a comprehensive jitter budget analysis to find and correct sources of jitter as well as to quickly and accurately predict Bit Error Ratio performance -- all before committing the design to fabrication and production."
The Agilent Signal Integrity Verification Toolkit contains patented technology used in Agilent's real-time sampling oscilloscopes for accurate jitter characterisation.
ADS is the first and only EDA tool in the industry that provides diagnostic jitter analysis tools integrated into a high-speed channel design flow.
This new release of Agilent's ADS also provides significant enhancements to its serialiser/deserialiser, or SERDES, modelling capability.
The new library of SERDES components available with ADS includes 8B10B encoders/decoders; 64B66B encoders and decoders with and without scrambling; non-adaptive and adaptive feed forward and decision feedback equalizers, using a wide variety of tap optimisation algorithms; and a new digital signal source capable of producing a de-emphasis waveform with random and periodic jitter modulation and transition wave shaping.
The Agilent ADS offers a complete set of front-to-back simulation and layout tools as well as instrument links for RF and microwave IC design in a single, integrated design flow.
Today, it is the only EDA software platform that can simulate a serial link consisting of models for frequency-domain interconnect, time-domain driver/receiver, physical layout, SERDES, compiled and scripted MATLAB-based functions, System-C, Verilog-A, HDL, and C++.
The seamless signal flow across this wide spectrum of simulation technology allows designers to fully characterise a high-speed serial link and accurately determine BER and jitter performance.