Home > Tunnelling Field Effect Transistors to slash MCU power demands

Tunnelling Field Effect Transistors to slash MCU power demands

Editorial
article image The TFET can be applied into some circuit blocks to achieve significant power reductions in microcontrollers.

TOSHIBA is developing Tunnelling Field Effect Transistors (TFET) which use a new operating principle to achieve ultra-low power draws.

According to Toshiba, it is developing two different TFETs using a CMOS platform compatible process. The TFET can be applied into some circuit blocks to achieve significant power reductions in microcontrollers.

Toshiba presented the TFETs on September 9th and 10th in three presentations at the 2014 Solid State Devices and Materials (SSDM) in Tsukuba, Japan. Two presentations were based on joint research with the Collaborative Research Team Green Nanoelectronics Center (GNC) at the National Institute of Advanced Industrial Science and Technology (AIST).

TFETs which use an operating principle based on the quantum tunneling effect have attracted much attention, being the technology most likely to achieve ultra-low power LSI operation instead of conventional MOSFETs.

New materials introduced recently, such as III-V compound semiconductors, have been investigated for use in TFETs. However, until now it has been difficult to implement such materials into current CMOS platforms.

Toshiba has addressed this problem by optimising TFET properties for some of key circuit blocks using common CMOS process. This approach enables simple installation of TFET into existing production line.

Toshiba has developed two types of silicon-based TFET, one for logic circuits with ultra-low leakage current and optimised ON current, the other for SRAM circuits with extremely low transistor characteristics variation.

Both utilise vertical type tunneling operation to enhance tunneling properties. In addition, the logic TFET employs precisely controlled epitaxial material growth process for tunnel junction formation with carbon and phosphorus doped Si.

The Si/SiGe hetero junction configuration has also been optimised.

As a result, the device achieves an ON current two orders of magnitude higher than a Si TFET, which keeps same ultra-low OFF current, both in N and P-type TFET.

For the SRAM type TFET development, Toshiba has proposed a novel TFET operation architecture which dispenses with the need to form a structural tunnel junction. This eliminates process variability.

Toshiba says it will be targeting commercial production and use of these TFETs by 2017.

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