SONY is increasing its production capacity for stacked CMOS image sensors.
Sony is investing in its Nagasaki Technology Centre and the Kumamoto Technology Centre from the second half of the current fiscal year in a bid to reinforce Nagasaki TEC’s layering process production capabilities, as well as Kumamoto TEC’s mastering process facilities.
The layering process involves layering semiconductor chips containing back-illuminated structure pixels with semiconductor chips containing the circuit for signal processing. Mastering refers to the manufacture of photodiodes and wiring processes.
This follows from a January 2014 announcement where Sony announced plans to establish and invest in the Yamagata Technology Centre, a facility used to conduct the mastering process.
The current investment is expected to enable Sony to complete subsequent stages of production, including the layering process, at Nagasaki TEC on semiconductor chips that have undergone the mastering process at Yamagata TEC, providing Sony with a fully integrated production system for stacked CMOS image sensors.
In the mid to long term, Sony plans to increase its total image sensor production capacity to approximately 75,000 wafers per month. It currently has capacity to produce approximately 60,000 wafers per month. This will increase to 68,000 wafers per month in August 2015.
Stacked CMOS image sensors deliver superior image quality and advanced functionality, together with compact size. Demand for these image sensors is anticipated to further increase, particularly within the expanding market for mobile devices such as smartphones and tablets.
CMOS image sensors layer, in a stacked structure, the pixel section, containing back-illuminated structure pixels, onto chips containing the circuit for signal processing, in contrast to the supporting substrates used in conventional back-illuminated CMOS image sensors.