Western Digital company and enterprise storage leader HGST has presented a new architecture for solid state drives (SSDs) that enables applications to provide faster insights to the data-intensive questions of tomorrow.
The demonstration proved that unprecedented SSD performance levels could be achieved by utilising a combination of HGST’s new, latency-optimised interface protocols with next-generation non-volatile memory components.
The SSD demonstration utilised a PCIe interface and delivered three million random read IOs per second of 512 Bytes each when operating in a queued environment and a random read access latency of 1.5 microseconds (us) in non-queued settings. Much faster than existing Flash based SSDs, the performance has resulted in a new class of block storage devices.
Steve Campbell, chief technology officer, HGST explained that the PCM SSD demonstration was a great example of how HGST has set the pace of the rapidly evolving storage industry. He commented that the new technology was the result of several years of research and advanced development aimed at delivering new levels of acceleration for enterprise applications. The combination of HGST’s low-latency interface protocol and next-generation non-volatile memories creates exciting opportunities for new software and system architectures that HGST is exploring with their customers and industry partners.
Applications for future non-volatile memory in SSDs
The memory used in this SSD consists of Phase Change Memory (PCM) components with a capacity of 1Gb. PCM is one of several new classes of high-density, non-volatile memories that exhibit dramatically faster read access times when compared to NAND Flash memory.
In order to fully expose the capabilities of these new memory technologies to the server system and its software applications, HGST has also developed a low-latency interface architecture that is fully optimised for performance and is agnostic to the specific underlying memory technology. HGST used its controller expertise to integrate the 45 nm 1Gb PCM chips to build a prototype full height, full length PCIe Gen 2x4 SSD card.
To achieve latencies close to 1us, HGST devised, in conjunction with researchers at the University of California, San Diego, a new communication protocol, which was introduced earlier this year at the 2014 Usenix conference on File and Storage Technologies (FAST).
A new class of storage
The emerging NVMs’ read latency is shorter by more than two orders of magnitude over NAND Flash, which is a major advantage for the new technology. To harness this intrinsic advantage, new controller and interface technologies are needed. The current NVMe protocol is not a problem in the context of NAND Flash but will be inadequate for these emerging NVM technologies that will introduce a new class of storage into the data centre ecosystem.